1. Field of the Invention
The present invention relates to a signal processing method for a Global Positioning System GPS receiver.
2. Prior Art
Some of the signals transmitted from satellites implemented in a Global Positioning System, hereinafter referred to as GPS, are available for commercial use. One such signal is a signal where the carrier frequency is phase-modulated by navigation data including information on the orbit of the satellite and is then further spread spectrum modulated by a C/A (Clear acquisition) code unique to the satellite.
The GPS receiver generates a code synchronized with the C/A code of the received signal for performing inverse spread spectrum of the received signal. A carrier frequency is then generated and synchronized with the carrier frequency of the received signal to reproduce the navigation data.
The GPS receiver includes an I register, Q register, and a carrier generating circuit for performing synchronous tracking of the carrier frequency with the aid of a Costas loop. The GPS receiver also includes an E register, L register, and a code generating circuit for performing synchronous tracking of code with that aid of a Delay Lock Loop (DLL).
The carrier frequency and the code generated in the receiver are supplied to the I register and Q register in order to determine a correlation with the received signal. The frequency of a carrier and the frequency of the code generated in the receiver are varied to search for a peak value of the correlation between the received signal so that the signal from a desired satellite is properly acquired.
After the signal from the GPS satellite has been acquired, the phase difference between the received signal and the carrier frequency generated in the receiver is determined based on the contents of the I register and Q register in order to control the carrier generating circuit to perform synchronous tracking of the carrier component of the received signal. At the same time, a phase difference between the code of the received signal and the code generated in the receiver is determined based on the contents of the E register and L register in order to control the code generating circuit to perform synchronous tracking of the code component of the received signal.
FIGS. 4 and 5 illustrate the RF circuit and signal processing circuit, respectively, as used in a prior art GPS receiver.
In FIG. 4, the radio wave from a GPS satellite is received via an antenna 1 and is then amplified by a low noise amplifier 2. The amplifier signal is then mixed with the output of a local oscillator 4 by a mixer 3 which converts the amplifier signal into an intermediate frequency. The intermediate frequency passes through an IF band-pass filter 5 which rejects unwanted noise and interference in the signal. The intermediate frequency signal is then amplified by an IF amplifier 6. Finally, the intermediate frequency is one-bit quantized by a limiter 7 before being output as an IF signal to the signal processing circuit in FIG. 5.
A reference oscillator 8 supplies a reference signal to the local oscillator 4. The local oscillator 4 is implemented in the form of Phase Locked Loop (PLL) which is locked on the reference signal from the reference oscillator 8. The Phase Locked Loop provides the local oscillator frequency to the mixer 3 for converting the signal from the satellite into an intermediate frequency signal. The reference oscillator 8 also supplies a reference clock to the signal processing circuit in FIG. 5.
In FIG. 5, the IF signal is supplied to an EXOR (Exclusive OR) gate 1 where the IF signal is multiplied with the code signal from the code generating circuit 12. The coincidence of each bit of code between the code of the IF signal and the code generated in the receiver is determined so that the output of EXOR has no code component when the code of the IF signal and the generated code are the same.
The output of the EXOR 1 is directed to the UP terminals of an I counter and Q counter. The I counter 13 and Q counter 14 take the form of a synchronous up/down counter. The counters 13 and 14 are incremented on the rising edge of a clock signal supplied to CK terminal when the input to the UP terminal is a logic 1. Correspondingly, the counters 13 and 14 count down when the input to UP terminal is a logic 0. The carrier generating circuit 15 generates clock signals ICK and QCK with the same frequency as predetermined by a CPU 16. The clock signal ICK is 90 degrees out of phase with the clock signal QCK. The clock signals ICK and QCK are supplied to the I counter 13 and Q counter 14, respectively.
At the end of each code signal cycle the values of the I counter 13 and the Q counter 14 are loaded into the I register 17 and the Q register 18, respectively. The contents of the registers are transferred to the CPU 16 via a data bus. During synchronous tracking of the signal, the CPU 16 manipulates the values in the I register and Q register in order to determine the phase difference I between the IF signal and the clock signal ICK and the phase difference Q between the IF signal and the clock signal QCK. During carrier acquisition, the CPU calculates the value of I.sup.2 +Q.sup.2 to determine the signal strength of the received signal.
The code generating circuit 12 generates three signals synchronized with the code component of the received signal; a CODE signal in phase with code component in the received signal, an EARLY signal with a phase which is 0.5 chip leading with respect to the phase of CODE signal by 0.5 chips, and a LATE signal with a phase which lags the phase of the CODE signal by 0.5 chips. The content of the original C/A code signal received from the satellite is provided to the code generating circuit 12 by the CPU 16, and the contents of the three synchronized signals generated by the code generating circuit 12 are identical to the contents of the original C/A code.
The CPU controls the CODE signal, EARLY signal, and LATE signal so that the phases of these signals are varied to lead or lag by a predetermined value as described above. The code generating circuit 12 also generates an EPOCH signal synchronized with the CODE signal and supplies it to the counter controlling circuit 19 and CPU 16. The EPOCH signal is set with a logic 1 value at the beginning of each CODE signal cycle and serves as a reference signal for controlling counters and registers.
The IF signal is compared with the clock signal QCK supplied by the carrier generating circuit 15 by the EXOR circuit 20. The resulting signal output by the EXOR circuit 20 is then compared with the EARLY signal supplied from the code generating circuit 12 by the EXOR circuit 21 and likewise compared with the LATE signal by the EXOR circuit 22. The output of the EXOR circuit 21 is supplied to the UP terminal of E counter 23, and the output of the EXOR circuit 22 is supplied to the UP terminal of the L counter 24. The rising edge of the clock signal ELCK output from the clock generating circuit 27 causes the E counter 23 and L counter 24 to count up when the UP terminal is a logic 1, and count down when the UP terminal is a logic 0.
At the end of each code signal cycle the values of the E counter 23 and L counter 24 are stored into the E register 25 and L register 26, respectively. The contents of the E register 25 and L register 26 are then transferred to the CPU 16 via the data bus. The contents of the E register 25 and L register 26 represent the degrees of correlation between the IF signal and the LATE signal. The CPU 16 calculates the difference between the contents of the E register and L register during synchronous tracking of code to determine the phase difference between the code component in the IF signal and the CODE signal output from the code generating circuit 12.
The four counters 13, 14, 23, and 24 each include an enable terminal EN and a clear terminal CL for controlling the counting operation of these counters. A logic 1 supplied to the EN terminal enables the counting operation of the counters and a logic 0 inhibits the counting operation of the counters. A logic 1 supplied to the CL terminals causes the counters to clear to 0 on the rising edge of the clock signal at the CK terminal, while a logic 0 allows the value in the counters to remain unchanged.
The four registers 17, 18, 25, and 26 each include a load terminal LD so that the registers latch a value supplied to an input terminal Dn of the registers on the rising edge of the signal supplied to the LD terminal. The values of the registers remain the same until the signal supplied to the LD terminal goes high again irrespective of any changes in the signal level at the input terminal Dn after the value at the input terminals Dn has been latched.
The counter controlling circuit 19 outputs the enable signal EN, the clear signal CL, and the load signal LD to the respective counters and registers. These signals are based on the EPOCH signal supplied from the code generating circuit 12. The signals EN and CL are used for the respective counters while the signal LD is used for the respective registers. The counters perform counting operation by counting up or down during the period of C/A code. The value of the counters is latched by the corresponding registers on the rising edge of the load signal LD at the end of each code signal cycle.
The EPOCH signal is output from the code generating circuit 12 in a timed relation with the beginning of each code signal cycle to the counter controlling circuit 19 so that the EN signal can be set to a logic 0 in order to halt operation of the respective counters. The output of the load signal LD is then set to a logic 1 so that the values of the respective counters can be latched into the corresponding registers. After the values of the counters have been latched by the corresponding registers, the counter controlling circuit 19 outputs the clear signal CL to the counters in order to clear the contents of the counters. The EN signal is then set to a logic 1 which causes the counters to resume their counting operations for the next cycle of the C/A code.
The clock generating circuit 27 provides a clock signal ELCK and a master clock signal MCK, which are based on the reference clock signal supplied by the reference oscillator 8 in the RF circuit in FIG. 4. The master clock MCK is supplied to the code generating circuit 12, carrier generating circuit 15, and counter controlling circuit 19 while the clock ELCK is supplied to the E counter 23 and L counter 24.
The CPU 16 executes the receiver-controlling program stored in the ROM 28 by the use of the RAM 29. The EPOCH signal is input to the interrupt terminal INT of the CPU in order to activate the interruption handling program of the CPU 16. The interruption handling program causes the CPU to read in the contents of the respective registers according to the timing supplied by the EPOCH signal.
Prior to the recognition of a signal from a satellite, the CPU 16 controls the carrier generating circuit 15 so that GPS receiver can search for the carrier and the C/A code of the received signal. The code generating circuit 15 is also controlled by the CPU 16 so that the GPS receiver can search for the phase of the C/A code of the received signal. The frequency range in which the search or carrier frequency is conducted is dictated by the Doppler frequency range of the signal from the satellite and the frequency error of the reference oscillator 8. The search for the phase of the C/A code is conducted for a length of time equal to one cycle of C/A the code signal, i.e., 1023 chips.
During the search operation, the CPU 16 examines the magnitudes of correlation for a peak value at a carrier frequency while varying the phase of the code by one chip at a time. Upon completing the search for 1023 chips, the CPU increases the thus determined the carrier frequency by a predetermined amount and conducts a search for the phase of the C/A code at the new carrier frequency. One millisecond is required to detect a value of correlation of a code signal and this time is equal to the amount of time necessary to complete one cycle of the code signal.
Therefore the time required for a complete search of the frequency and phase is equal to the total number N of frequency increments multiplied by the time necessary to search through 1023 chips, i.e., 1023N milliseconds. The CPU 16 calculates the values indicative of correlation, i.e., values of I.sup.2 +Q.sup.2 and I + Q from the contents in the I register and Q register. When a calculated value exceeds a predetermined corresponding threshold value, the CPU 16 determines that the signal from the satellite has been properly acquired, and the CPU 16 terminates search operation to subsequently perform the tracking operation of the received signal.
During synchronous tracking operation of the received signal, the CPU 16 calculates the phase difference between the received signal and the carrier signal generated by the carrier generating circuit 15 based on the values in the I register 17 and the Q register 18. The calculated values then undergo an arithmetic operation by the loop filter. Using the results of arithmetic operation by the loop filter, the CPU 16 controls the carrier generating circuit 15 so that the frequency of the carrier signal generated in the receiver follows the frequency of the received signal. At the same time, the CPU 16 determines the phase difference between the C/A code of the received signal and the code signal generated by the code generating circuit 12 based on the values in the E register 25 and L register 26. The calculated phase difference then undergoes an arithmetic operation by a loop filter. Using the result of the arithmetic operation by the loop filter, the CPU 16 controls the code generating circuit 12 so that the phase of code follows that of the received signal.
The search operation is conducted by the prior art signal processing circuit illustrated in FIG. 5 on the signal being received for both carrier frequency and the phase of code. Thus, the time required for calculating the correlations for carrier frequency and the phase of the code should be substantially equal to one cycle of the code. Times shorter than one cycle of the code result in a spurious peak in correlation value which in turn causes error detection during phase search. Therefore, the time required for calculating correlation is primarily dictated by one cycle of the code.
This implies that the time required to properly acquire the signal from a satellite in the worst case is as long as the time of one cycle times the number of steps dictated by the range in which the carrier frequency and code phase are searched for. Moreover, the use of an inexpensive reference oscillator with a large frequency error requires a frequency search in a wider range which in turn causes longer acquisition time.